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1、StaticTimingAnalysisforNanometerDesignsAPracticalApproachJ.Bhasker?RakeshChadhaStaticTimingAnalysisforNanometerDesignsAPracticalApproachJ.BhaskerRakeshChadhaeSiliconCorporationeSiliconCorporation1605N.CedarCrestBlvd.890MountainAveSuite615NewProvidence,NJ0
2、7974,USAAllentown,PA18103,USArchadha@esilicon.comjbhasker@esilicon.comISBN978-0-387-93819-6e-ISBN978-0-387-93820-2DOI:10.1007/978-0-387-93820-2LibraryofCongressControlNumber:2009921502?SpringerScience+BusinessMedia,LLC2009Allrightsreserved.Thisworkmaynotb
3、etranslatedorcopiedinwholeorinpartwithoutthewrittenpermissionofthepublisher(SpringerScience+BusinessMedia,LLC,233SpringStreet,NewYork,NY10013,USA),exceptforbriefexcerptsinconnectionwithreviewsorscholarlyanalysis.Useinconnectionwithanyformofinformationstor
4、ageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilarmethodologynowknownorhereafterdevelopedisforbidden.Theuseinthispublicationoftradenames,trademarks,servicemarksandsimilarterms,eveniftheyarenotidentifiedassuch,isnottobetakenasane
5、xpressionofopinionastowhetherornottheyaresubjecttoproprietaryrights.Whiletheadviceandinformationinthisbookarebelievedtobetrueandaccurateatthedateofgoingtopress,neithertheauthorsnortheeditorsnorthepublishercanacceptanylegalresponsibilityforanyerrorsoromiss
6、ionsthatmaybemade.Thepublishermakesnowarranty,expressorimplied,withrespecttothematerialcontainedherein.Somematerialreprintedfrom“IEEEStd.1497-2001,IEEEStandardforStandardDelayFormat(SDF)fortheElectronicDesignProcess;IEEEStd.1364-2001,IEEEStandardVerilogHa
7、rdwareDescriptionLanguage;IEEEStd.1481-1999,IEEEStandardforIntegratedCircuit(IC)DelayandPowerCalculationSystem”,withpermissionfromIEEE.TheIEEEdisclaimsanyresponsibilityorliabilityresultingfromtheplacementanduseinthedescribedmanner.Libertyformatspecificati
8、onandSDCformatspecificationdescribedinthistextarecopyrightSynopsysInc.andarereprintedaspertheSynopsysopen-sourcelicenseagreement.TimingreportsarereportedusingPrimeTimewhicharecopyright?<2007>Synopsys,Inc.Usedwithper
