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1、quartusii中常見warning及解決方法(轉(zhuǎn)載)（QuartusII中常見警告及解決方法（轉(zhuǎn)載））Supportoriginal!Ireprinted,youcandownloadfree1.Foundclock-sensitive,change,during,active,clock,edge,at,time,
2、nization,loading,etc.)changesimultaneouslyontheedgeoftheclock.Aclocksensitivesignalcannotchangeattheedgeoftheclock.Theconsequenceisthattheresultisincorrect.Measures:editvectorsourcefile2.Verilog,HDL,assignment,warning,at,:truncated,value,with,size,,to,m
3、atch,,size,of,target(Reason:inHDLdesign,thenumberoftargetsisset,suchas:reg[4:0]a,anddefaultto32bits,thenumberofdigitstotherightsizeMeasure:iftheresultiscorrect,itneedsnocorrection.Ifyoudon'twanttoseethiswarning,youcanchangethenumberofsettings3.All,reachable,assig
4、nments,to,data_out(10),assign,'0',register,removed,by,optimizationReason:aftertheoptimizerhasbeenoptimized,theoutputportisnolongerfunctional4.Following9,pins,have,nothing,GND,or,VCC,driving,datain,port-changes,to,this,,connectivity,may,change,results,fittingReason:ninthf
5、eet,emptyorgroundedorconnectedtothepowersupplyMeasures:sometimestheoutputportisdefined,buttheoutputisdirectlyassignedto'0',whichwillbegroundedandassigned'1'tothepowersupply.Iftheseportsareusedinyourdesign,youcanignorethesewarning5.Found,pins,functioning,as,undefined,cloc
6、ks,and/or,memory,enablesReason:youhavenoconstraintinformationasthePINoftheclock.YoucansetthesettingsforthecorrespondingPIN.Mainlyreferstosomeofyourpininthecircuitplayedaroleintheclocktube,suchastheflip-flopCLKpin,andthispinhasnoclockconstraint,soQuartusIICLKasundefinedcl
7、ock.Measures:ifCLKisnotaclock,canadd"notclock"constraint;ifitis,canbeaddedinclocksetting;insomeoftheclockrequirementsarenotveryhigh,youcanignorethiswarningormodifiedhere:Assignments>Timinganalysissettings...Individualclocks>>.....6.Timing,characteristics,of,device,EPM570
8、T144C5,are,preliminaryReason:becauseMAXIIisarelativelynewcomponent,thetiminginQuartusIIisnotaformalvers
