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1、VHDL快速參考手冊(cè)PRIMARYDESIGNUNITMODELSTRUCTUREEach?VHDLdesignunitcomprisesan"entity"declarationandoneormore"architectures".Eacharchitecturedefinesadifferentimplementationormodelofagivendesignunit.Theentitydefinitiondefinestheinputsto,andoutputsfromthemodule,
2、andany"generic"parametersusedbythedifferentimplementationsofthemodule.EntityDeclarationFormat???entity?name?is???????port(portdefinitionlist);--input/outputsignalports???????generic(genericlist);??--optionalgenericlist???endname;Portdeclarationformat:po
3、rt_name:modedata_type;Themodeofaportdefinesthedirectionsofthesingalsonthatpirt,andisoneof:in,out,buffer,orinout.PortModes:Aninportcanbereadbutnotupdatedwithinthemodule,carryinginformationintothemodule.(Aninportcannotappearonthelefthandsideofasignalassig
4、nment.)Anoutportcanbeupdatedbutnotreadwithinthemodule,carryinginformationoutofthemodule.(Anoutportcannotappearontherighthandsideofasignalassigment.)Abufferportlikewisecarriesinformationoutofamodule,butcanbebothupdatedandreadwithinthemodule.Aninoutportis
5、bidirectionalandcanbebothreadandupdated,withmultipleupdatesourcespossible.·NOTE:Abufferisstrictlyanoutputport,i.e.canonlybedrivenfromwithinthemodule,whileinoutistrulybidirectionalwithdriversbothwithinandexternaltothemodule.Example??entitycounteris??????
6、?port(Incr,Load,Clock:in????bit;?????????????Carry:????????????out???bit;?????????????Data_Out:?????????bufferbit_vector(7downto0);?????????????Data_In:??????????in????bit_vector(7downto0));??endcounter;Genericsallowstaticinformationtobecommunicatedtoab
7、lockfromitsenvironmentforallarchitecturesofadesignunit.Theseincludetiminginformation(setup,hold,delaytimes),partsizes,andotherparameters.Example???entityand_gateis???????port(a,b:in?bit;????????????c:??outbit);???????generic(gate_delay:time:=5ns);???end
8、and_gate;ArchitectureAnarchitecturedefinesoneparticularimplementationofadesignunit,atsomedesiredlevelofabstraction.?architecturearch_nameofentity_nameis??????...?declarations...??begin??????...?concurrentstatements?...??endDeclar