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1、基于JPEG2000的小波變換和EBCOT的研究與硬件設(shè)計AbstractWiththedevelopmentofInternetandmultimediatechnology,theinformationbecomesmoreandmore,andthelimitedstorageandbandwidthisbecomethebottleneck.Soitisnecessaryfortheeffectiveprocessingandcompressionofinformation.ThelateststillimagecompressionstandardJPEG200
2、0adoptsDiscreteWaveletTransformandEmbeddedBlockCodingwithOptimizedTruncation(EBCOT),andachievesmuchbettercodingefficiencyandimagequalitythanthetraditionalmethods.Withitsexcellentperformanceandprominentfeatures,JPEG2000willnodoubtbecomethemain-streamintheimagecompressionfieldinthefuture.Bu
3、titishardforhardwareimplementationofJPEG2000.HighattentionispaidtodesignVLSIarchitectureforDWTandEBCOTimplementationwithreal-time,lowareaandenergydissipation.Firstly,thisthesisanalyzestheprocessofJPEG2000encoder.ThenthisdissertationdeeplyaccessedthehardwareimplementationtechniquesforDWT,b
4、itplanecodingandbinaryarithmeticcodecusedinJPEG2000.AsfortheVLSIimplementationofdiscretewavelettransform(DWT),therowbasedmethodandparallelarchitectureisadoptedforthe2-DDWT,whichmakesboththetransformspeedandtheefficiencyincrease.Withcombiningthedata-extensionprocedureintotheDWTcore,thememo
5、ryrequirementandmemoryaccessofDWTcanbereduced.Andthearchitecturecanaccomplicemulti-levelDWTforthewholeimageusingonly6rowsofinnersingle-portRAM.Asforthehardwareimplementationofbitplanecoding,abitplanecoderbasedoncoding-passparallelprocessingispresented.Thethreescanproceduresofthealgorithmf
6、orbitplanecodinginJPEG2000isincorporatedintoonescanprocedure.Theacceleratorisefficient,andareaisnotlarge.AsfortheVLSIimplementationofbinaryarithmeticcodec,thebinaryarithmeticcodecbasedonthree-pipelinearchitectureispresented,whichimprovestheencodingefficiencywithencodingonedataeveryclock.A
7、tlast,thethreeproposedarchitectureisimplementedinVerilogHDL.Theresultofsimulationandsynthesisoftheproposedarchitectureprovesthedesign.Keywords:DWT；LiftingScheme；EBCOT；JPEG2000II碩士學(xué)位論文插圖索引圖2.1JPEG2000編碼器結(jié)構(gòu)框圖····························································
