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1、第十三講 微處理器接口芯片設(shè)計(jì)實(shí)例--可編程并行接口芯片設(shè)計(jì)實(shí)例曲阜師范大學(xué)電氣信息與自動(dòng)化學(xué)院本講主要內(nèi)容8255的引腳及內(nèi)部結(jié)構(gòu)8255的工作方式及其控制字8255的結(jié)構(gòu)設(shè)計(jì)8255芯片的VHDL語(yǔ)言描述8255芯片VHDL語(yǔ)言描述模塊仿真8255的引腳及內(nèi)部結(jié)構(gòu)外部引腳內(nèi)部結(jié)構(gòu)控制字LIBRARYIEEE;USEIEEE.STD_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPPIIS使用庫(kù)PORT(RESET,RD,WR,CS,A0,A1:INST
2、D_LOGIC;PA:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);PB:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);PCL:INOUTTD_LOGIC_VECTOR(3DOWNTO0);PCH:INOUTSTD_LOGIC_VECTOR(3DOWNTO0);D:INOUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDPPI;實(shí)體描述構(gòu)造體描述ARCHITECTURERTLOFPPIISSIGNALINTERNAL_BUS_OUT:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALIN
3、TERNAL_BUS_IN:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALST,AD,FLAG:STD_ULOGIC_VECTOR(1DOWNTO0);SIGNALCTRREG:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALPA_LATCH,Pb_LATCH,Pc_LATCH:CTRREG:STD_ULOGIC_VECTOR(7DOWNTO0);讀進(jìn)程BEGINPROCESS(RD,CS)Beginst<=cttreg(3)&cttreg(0);if(cs=‘0’andrd=‘0’)thenif(a0=‘0’an
4、da1=‘0’andcttreg(4)=‘1’)theninternal_bus_in<=pa;elsif(a0=‘0’anda1=‘0’andcttreg(1)=‘1’)theninternal_bus_in<=pb;elsif(a0=‘0’anda1=‘1’andst=“01”)theninternal_bus_in(3downto0)<=pcl(3downto0);elsif(a0=‘0’anda1=‘1’andst=“10”)theninternal_bus_in(7downto4)<=pch(3downto0);elsif(a0=‘0’anda1
5、=‘1’andst=“11”andctrreg(7)=‘1’)theninternal_bus_in（3downto0）<=pcl(3downto0);internal_bus_in（7downto4）<=pch(3downto0);process(cs,wr,reset)variablectrregF:std_ulogic;variablebctrreg_v:std_ulogic_vector(3downto0);beginif(cs='0'andwr='0')thenad<=a1&a0;ctrregF:=d(7);iternal_bus_out<=d;
6、endif;if(reset='1')thenpa_latch<="00000000";pb_latch<="00000000";pc_latch<="00000000";ctrreg<="10011011"bctrreg_v:="0000";ctrregF:='0';elsif(wr'eventandwr='1')thenif(ctrregF='1'andad="11"andcs='0')thenctrreg<=internal_bus_out;elsif(ctrreg(7)='1'andad="00"andcs='0')thenpa_latch<=in
7、ternal_bus_out;elsif(ctrreg(7)='1'andad="01"andcs='0')thenpb_latch<=internal_bus_out;elsif(ctrreg(7)='1'andad="10"andcs='0')thenpc_latch<=internal_bus_out;elsif(ctrregF='0'andad="11"andcs='0')thenbctrreg:=internal_bus_out(3downto0);casebctrreg_viswhen"0000"=>pc_latch(0)<='0';when"
8、0010"=>pc_latch(1)<='0';when"0100
