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1、時序分析原理:需要對器件布線中的每一條路徑進行與時序設置/需求相關的分析(比門級仿真和板級測試更方便快捷)不過這種時序分析事先需要設計者輸入時序要求和時序例外(這個需求用來指求布線器的palcement&nnning."J以將這個輸入需求Launch&LatchEdgesDATA―XDataValidXLatchEdgeLaunchEdge:theedgewhich“l(fā)aunches"thedatafromsourceregisterLatchEdge:theedgewhichlatches"thedataat
2、destinationregister(withrespecttothelaunchedge,selectedbytiminganalyzer:typically1cycle)Setup&HoldDATAPRErcUQ>CLRCLKCLK?suThDATAXValidXSetup:TheminimumtimedatasignalmustbestableBEFOREclockedgeHold:TheminimumtimedatasignalmustbestableAFTERclockedgeTogether,t
3、hesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.DataArrivalTime■ThetimefordatatoarriveatdestinationregistersDinputDataArrivalTime=launchedge+Tclk1+Tco+TdataClockArrivalTime■Thetimeforclocktoarriveatdestinationregi
4、ster'sclockinputClockArrivalTime=latchedge+Tcl<2DataRequiredTime?Setup■TheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterDataRequiredTime=ClockArrivalTime-TSL1?SetupUncertaintyDataRequiredTime■HoldTheminimumtimerequiredforthedatatogetlatc
5、hedintothedestinationDataRequiredTime=ClockArrivalTime+Th+HoldUncertaintySetupSlack■Themarginbywhichthesetuptimingrequirementismet.Itensureslauncheddataarrivesintimetomeetthelatchingrequirement.從上圖可以看出,止的setupslack代表時序得到滿足,而負的setupslack則是時序沒有得到滿足的表現(xiàn)。HoldSlac
6、k■Themarginbywhichtheholdtimingrequirementismet.Itensureslatchdataisnotcorruptedbydatafromanotherlaunchedge.CLKREG1.CLKREG1.QREG2.DREG2.CLK同樣從以上的時序圖可以看出,正的holdslack代表吋序得到滿足,而負的holdslack時序則不滿足時序。