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1、QuartusII與Modelsim仿真的區(qū)別：用QuartusII寫了一個隔直濾波器，運(yùn)用QuartusII9.1自帶的波形仿真，仿真結(jié)果與matlab仿真后的結(jié)果比較近似。仿真結(jié)果為：下圖為testbench部分代碼：LIBRARYieee;USEieee.std_logic_1164.all;useIEEE.STD_LOGIC_ARITH.ALL;useieee.std_logic_unsigned.all;useieee.std_logic_signed.all;ENTITYgezhi_filter_vhd_tstISENDgezhi_filter_vhd_tst;A
2、RCHITECTUREgezhi_filter_archOFgezhi_filter_vhd_tstISconstantclk_period:time:=10ns;--constants--signals);ENDCOMPONENT;BEGINi1:gezhi_filterPORTMAP(--listconnectionsbetweenmasterportsandsignalsclk,clr,d00,d02,d04,d06,d11,d22,d_sf0,d_sf10,d_sf20,d_sf30,d_sf40,d_sf120,d_sf340,din_x,dou_y);clk_ge
3、n:PROCESS--variabledeclarationsBEGINclk<='0';--codethatexecutesonlyoncewaitforclk_period/2;clk<='1';waitforclk_period/2;ENDPROCESS;clr_gen:PROCESSBEGIN--clr<='1';--codeexecutesforeveryeventonsensitivitylist--waitforclk_period/4;clr<='0';WAIT;ENDPROCESS;din_x_gen:PROCESSBEGINdin_x<=CONV_STD_
4、LOGIC_VECTOR(256,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(-12,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(32,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(39,18);--codethatexecutesonlyoncewai
5、tforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(-128,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(512,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(520,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(15,
6、18);--codethatexecutesonlyoncewaitforclk_period;ENDPROCESS;ENDgezhi_filter_arch;調(diào)用modelsim6.5SE仿真后的波形圖：仿真結(jié)果中，din_x是輸入，dou_y是輸出，modelsim結(jié)果中的紅線X代表未知輸出而不是0，導(dǎo)致最后的結(jié)果dou_y開頭都是0輸出，和Quartus仿真結(jié)果不同。解決辦法：加上上電復(fù)位，開始是clr=1全部清零。Testbench里clr激勵更改如下：clr_gen:PROCESSBEGINclr<='1';--codeexecutesforeveryeventon
7、sensitivitylistwaitforclk_period/4;clr<='0';WAIT;ENDPROCESS;Modelsim仿真結(jié)果，dou_y已經(jīng)和Quartus結(jié)果差不多了，但是也略有差別，不知道原因總結(jié)：調(diào)用QuartusII，端口default值是0，而調(diào)用modelsim，端口默認(rèn)未知X，所以程序一定要先在端口清零，否則導(dǎo)致錯誤輸出。
