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1、摘要伴隨著集成電路技術(shù)的發(fā)展，電子設(shè)計(jì)自動(dòng)化(EDA)逐漸成為重要的設(shè)計(jì)手段，已經(jīng)廣泛應(yīng)用于模擬與數(shù)字電路系統(tǒng)等許多領(lǐng)域。EDA的一個(gè)重要特征就是使用硬件描述語(yǔ)言(VHDL)來(lái)完成設(shè)計(jì)文件。誕生于1982年的VHDL語(yǔ)言是經(jīng)IEEE確認(rèn)的標(biāo)準(zhǔn)硬件描述語(yǔ)言，在電子設(shè)計(jì)領(lǐng)域受到了廣泛的接受。數(shù)字基帶信號(hào)的要求主要有兩點(diǎn)，第一是對(duì)各種代碼的要求，期望將原始信息符號(hào)編制成適合于傳輸用的碼型；第二則是對(duì)所選的碼型的波形的要求，期望波形適宜于在信道中傳輸。HDB3編碼是數(shù)字基帶信號(hào)傳輸中常用的傳輸碼型，因其具
2、有無(wú)直流成分，低頻成分少和連零位數(shù)目最多不超過(guò)三個(gè)等明顯的優(yōu)點(diǎn)，對(duì)時(shí)鐘信號(hào)的恢復(fù)十分有利而成為普遍使用的基帶傳輸碼之一。本設(shè)計(jì)是在QuartusII開(kāi)發(fā)環(huán)境下采用VHDL語(yǔ)言的，設(shè)計(jì)HDB3編碼器和譯碼器。根據(jù)編碼規(guī)則將譯碼器分為三個(gè)部分：插V模塊、插B模塊、單極性變雙極性模塊。根據(jù)譯碼規(guī)則，譯碼器只包含一個(gè)模塊。最后，對(duì)每個(gè)模塊進(jìn)行仿真，實(shí)現(xiàn)相應(yīng)功能后再進(jìn)行整體仿真。關(guān)鍵詞HDB3VHDL編碼譯碼IAbstractTheElectronicDesignAutomation(EDA)technol
3、ogyhasbecomeanimportantdesignmethodofanaloganddigitalcircuitsystemgrowing.OneimportantcharacteristicoftheEDAAsistheintegratedcircuitoneofthestandarddescriptionlanguagesvalidatedbyIEEE，whichwasfirstlyintroducedin1982.Anditwaswidelyusedbyelectronicdesig
4、nernow.Therequirementsofdigitalbasebandsignalsaretwopoints,Thefirstistherequirementofvariouscode,expectedthepreparationoftheoriginalinformationsymbolsusedtopatterninaformsuitablefortransmission;Thesecondistherequirementsofthepatternoftheselectedwavefo
5、rm,expectedwaveformsuitablefortransmissioninthechannel.TheHDB3codingschemeiscommonlyusedindigitalbasebandtransmission.TheHDB3code，whichhasfeaturesofzeroDCbiasviaalternatingpositive-negativevoltagelevelbitbybitandnomorethanthreecontinuous-zerobits，dedu
6、cesthepowerdissipationandmakesthereceivingdeviceeasytorecovertheclockinthetransmittedcodestream.somymajorcontentofgraduateddesignisdesigningbasedontheHDB3volume/decoderofVHDLlanguage，therequirementthatitwillreachisthebasicskillthatcanrealizeHDB3volume
7、/decoderfunctioninsoftwarecan，andcancoordinateentiredesign，makesureitreachtherequirementthatanticipated.ThisdesigninQuartusIIdevelopmentenvironmentusesVHDLlanguagetodesignHDB3encoderanddecoder.Accordingtotheencodingrules,therearethreepartsindecoder:in
8、sertthemoduleV,insertthemoduleB,theunipolarvariablebipolarmodule..Accordingtothedecodingrules,decodercontainsonlyonemodule.Finally,thesimulationofeachmodule,itachievethecorrespondingfunctionandthenachievethewholesimulation.KeywordsVHDLHDB3Enco
