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1、FPGAUSB_BLASTER原理圖與源程序??2008-02-2709:31:35
2、??分類：技術(shù)文章
3、??標(biāo)簽：
4、舉報(bào)
5、字號大中小?訂閱原理圖：?CPLD源程序：?LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;ENTITYjtag_logicIS?PORT?(??CLK:INSTD_LOGIC;???????--external24/25MHzoscillator??nRXF:INSTD_LOGIC;??????--FT245BMnRXF??nTXE:INSTD_LOGIC;??????--FT2
6、45BMnTXE??B_TDO:INSTD_LOGIC;?????--JTAGinput:TDOoflastdeviceinchain??nRD:OUTSTD_LOGIC;??????--FT245BMnRD??WR:OUTSTD_LOGIC;???????--FT245BMWR??B_TCK:BUFFERSTD_LOGIC;?--JTAGoutput:TCKtochain??B_TMS:BUFFERSTD_LOGIC;?--JTAGoutput:TMStochain??B_TDI:BUFFERSTD_LOGIC;?--JTAGoutput:toTDIoffirstdeviceinchain?
7、?D:INOUTSTD_LOGIC_VECTOR(7downto0)--FT245BMD[7..0]?);ENDjtag_logic;ARCHITECTUREspecOFjtag_logicIS?TYPEstatesIS?(??wait_for_nRXF_low,??set_nRD_low,??keep_nRD_low,??latch_data_from_host,??set_nRD_high,??bits_set_pins_from_data,??bytes_set_bitcount,??bytes_get_tdo_set_tdi,??bytes_clock_high_and_shift,?
8、?bytes_keep_clock_high,??bytes_clock_finish,??wait_for_nTXE_low,??set_WR_high,??output_enable,??set_WR_low,??output_disable?);??SIGNALcarry:STD_LOGIC;?SIGNALdo_output:STD_LOGIC;?SIGNALioshifter:STD_LOGIC_VECTOR(7DOWNTO0);?SIGNALbitcount:STD_LOGIC_VECTOR(8DOWNTO0);?SIGNALstate,next_state:states;?BEGI
9、N?--sm:PROCESS(nRXF,nTXE,state,D,bitcount,ioshifter,do_output)?sm:PROCESS(nRXF,nTXE,state,bitcount,ioshifter,do_output)?BEGIN??CASEstateIS?????--============================INPUT?????WHENwait_for_nRXF_low=>????IFnRXF='0'THEN?????next_state<=set_nRD_low;????ELSE?????next_state<=wait_for_nRXF_low;????
10、ENDIF;???????WHENset_nRD_low=>????next_state<=keep_nRD_low;??????WHENkeep_nRD_low=>????next_state<=latch_data_from_host;???????WHENlatch_data_from_host=>????next_state<=set_nRD_high;??????WHENset_nRD_high=>????IFNOT(bitcount(8DOWNTO3)="")THEN?????next_state<=bytes_get_tdo_set_tdi;????ELSIFioshifter(
11、7)='1'THEN?????next_state<=bytes_set_bitcount;????ELSE?????next_state<=bits_set_pins_from_data;????ENDIF;??????WHENbytes_set_bitcount=>????next_state<=wait_for_nRXF_low;??????--=======================
