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1、testbench顧名思義就是一個測試臺,它對外沒有接口,所以實體部分為空,但它要對要測試的器件提供激勵信號,這其實就是最簡單的testbench,以下是具體的操作步驟:1.首先基于QuartusII建立的一個新的工程,編譯通過,這其實就是我們要測試的源文件DUT(designundertest)counter.vhd.libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounterisport(clk:instd_logic;?????
2、reset:instd_logic;?????en:instd_logic;?????q:outstd_logic_vector(3downto0));endcounter;architecturebehaveofcounteris???signalq_n:std_logic_vector(3downto0);begin???process(clk,reset,en,q_n)???begin???????if(reset='1')then???????????q_n<=(others=>'0');--òì2???á????????elsi
3、frising_edge(clk)then???????????ifen='1'then???????????????q_n<=q_n+1;???????????endif;???????endif;???endprocess;???q<=q_n;endbehave;2.打開ModelSim,指定路徑為Quartus工程所在目錄;建立新的仿真工程,添加文件(DUT)。3.編譯DUT文件到仿真庫中(右鍵DUT,選擇compile).4.寫testbench文件(counter_tb.vhd)。首先選擇view-source-showlang
4、uagetemplates,然后選擇file-new-source-vhdl,雙擊creattestbench,選擇DesignUnitName為DUT文件,點擊finish,模板創(chuàng)建完成,然后右鍵取消readonly,自己添加測試信號。LIBRARYieee?;USEieee.std_logic_unsigned.all?;USEieee.std_logic_1164.all?;ENTITYcounter_tb?IS????constantClockPeriod:time:=40ns;END;?ARCHITECTUREcounter_t
5、b_archOFcounter_tbIS?componentcounteris???????port(clk:instd_logic;???????????reset:instd_logic;???????????en:instd_logic;???????????q:outstd_logic_vector(3downto0));???endcomponentcounter;???????????????signalclock,rst,en:std_logic;???signalq:std_logic_vector(3downto0);b
6、egin???CounterInstance:counterportmap(clock,rst,en,q);??????simProcess:process???begin???????rst<='1';???????waitfor50ns;???????rst<='0';???????waitfor1000ns;???????rst<='0';???endprocesssimprocess;??????en<='0'after0ns,???????'1'after50ns,???????'0'after850ns,???????'1'a
7、fter900ns;????????ClockProcess:process(clock,rst)???begin???????if(rst='1')then???????????clock<='0';???????else???????????clock<=notclockafterClockPeriod;???????endif;???endprocessClockProcess;???END;5.同樣把testbench文件編譯到仿真庫中。6.點擊simulate-startsimulation,選中design標(biāo)簽work庫下te
8、stbench文件,點擊ok。7.workspace窗口出現(xiàn)sim標(biāo)簽,右鍵testbench文件,選擇addtowave,然后點擊開始仿真按鈕即可。