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1、指令類型[31:26][25:21][20:16][15:11][10:6][5:0]R類型OpRsRtRdshamtfunct含義nop00000000000000000000000000000000空操作addu000000rsrtrd00000100001加（不帶溢出）subu000000rsrtrd00000100011減（不帶溢出）and000000rsrtrd00000100100與or000000rsrtrd00000100101或xor000000rsrtrd00000100110異或nor000000rsrtrd00000100111或非sllv000000r
2、srtrd00000000100邏輯左移變量srlv000000rsrtrd00000000110邏輯右移變量I類型OpRsRtimmediatebltz000001rs00000Immediate小于0轉(zhuǎn)移beq000100rsrtImmediate相等轉(zhuǎn)移bne000101rsrtImmediate不相等轉(zhuǎn)移addi001000rsrtImmediate加立即數(shù)andi001100rsrtImmediate與立即數(shù)ori001101rsrtImmediate或立即數(shù)lw100011rsrtImmediate取字sw101011rtrtImmediate存字J類型OpAddr
3、essj000010address無(wú)條件跳轉(zhuǎn)綜述：本設(shè)計(jì)選用了如下指令，基于此設(shè)計(jì)出了單周期MIPS處理器，并在單周期的基礎(chǔ)上添加了5級(jí)流水線設(shè)計(jì)出了帶五級(jí)流水線的MIPS處理器。第一部分單周期MIPS處理器一、代碼------------------------------------------------------------------------------------ModuleName:top_mips-Behavioral頂層模塊------------------------------------------------------------------
4、----------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitytop_mipsisport(reset:instd_logic;clk:instd_logic;ov:outstd_logic);endtop_mips;architectureBehavioraloftop_mipsissignals_pc:std_logic_vector(31downto0);---pc輸入signals_pc_i:s
5、td_logic_vector(31downto0);---pc輸出signals_command:std_logic_vector(31downto0);---指令signals_add1_pc:std_logic_vector(31downto0);---pc+1值signals_shift:std_logic_vector(27downto0);--指令低26位左移2位后值signals_jump_pc:std_logic_vector(31downto0);--絕對(duì)跳轉(zhuǎn)signals_regdst:std_logic;----控制信號(hào)signals_jump:std_l
6、ogic;signals_branch:std_logic;signals_memread:std_logic;signals_memtoreg:std_logic;signals_aluop:std_logic_vector(3downto0);signals_memwrite:std_logic;signals_alusrc:std_logic;signals_regwrite:std_logic;signals_opa:std_logic_vector(31downto0);----ALU操作數(shù)signals_opb:std_logic_vector(31downto0)
7、;----ALU操作數(shù)signals_reg_data:std_logic_vector(31downto0);--寄存器讀出的第二個(gè)數(shù)據(jù)signals_imm_data:std_logic_vector(31downto0);---低16位符號(hào)擴(kuò)展后signals_zero:std_logic;signals_alu_result:std_logic_vector(31downto0);signals_branch_pc:std_logic_vector(31downto0);----條件
