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1、指令類型[31:26][25:21][20:16][15:11][10:6][5:0]R類型OpRsRtRdshamtfunct含義nop00000000000000000000空操作addursrtrd00000加（不帶溢出）subursrtrd00000減（不帶溢出）andrsrtrd00000與orrsrtrd00000或xorrsrtrd00000異或norrsrtrd00000或非sllvrsrtrd00000邏輯左移變量srlvrsrtrd00000邏輯右移變量I類型OpRsRtimmediate
2、bltzrs00000Immediate小于0轉(zhuǎn)移beqrsrtImmediate相等轉(zhuǎn)移bnersrtImmediate不相等轉(zhuǎn)移addirsrtImmediate加立即數(shù)andirsrtImmediate與立即數(shù)orirsrtImmediate或立即數(shù)lwrsrtImmediate取字swrtrtImmediate存字J類型OpAddressjaddress無條件跳轉(zhuǎn)綜述：本設計選用了如下指令，基于此設計出了單周期MIPS處理器，并在單周期的基礎上添加了5級流水線設計出了帶五級流水線的MIPS處理器。第一
3、部分單周期MIPS處理器一、代碼------------------------------------------------------------------------------------ModuleName:top_mips-Behavioral頂層模塊----------------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;us
4、eIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitytop_mipsisport(reset:instd_logic;clk:instd_logic;ov:outstd_logic);endtop_mips;architectureBehavioraloftop_mipsissignals_pc:std_logic_vector(31downto0);---pc輸入signals_pc_i:std_logic_vector(31down
5、to0);---pc輸出signals_command:std_logic_vector(31downto0);---指令signals_add1_pc:std_logic_vector(31downto0);---pc+1值signals_shift:std_logic_vector(27downto0);--指令低26位左移2位后值signals_jump_pc:std_logic_vector(31downto0);--絕對跳轉(zhuǎn)signals_regdst:std_logic;----控制信號signa
6、ls_jump:std_logic;signals_branch:std_logic;signals_memread:std_logic;signals_memtoreg:std_logic;signals_aluop:std_logic_vector(3downto0);signals_memwrite:std_logic;signals_alusrc:std_logic;signals_regwrite:std_logic;signals_opa:std_logic_vector(31downto0);-
7、---ALU操作數(shù)signals_opb:std_logic_vector(31downto0);----ALU操作數(shù)signals_reg_data:std_logic_vector(31downto0);--寄存器讀出的第二個數(shù)據(jù)signals_imm_data:std_logic_vector(31downto0);---低16位符號擴展后signals_zero:std_logic;signals_alu_result:std_logic_vector(31downto0);signals_branc
8、h_pc:std_logic_vector(31downto0);----條件跳轉(zhuǎn)signals_1orbranch:std_logic_vector(31downto0);signals_ram_data:std_logic_vector(31downto0);signals_wr_data:std_logic_vector(31downto0);signals_mux:std_logic;sig
