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1、332.2系統(tǒng)的輸入、輸出端口以及寄存器清單及說明：CLK輸入時鐘方波信號端口KIN鍵盤按鍵輸入端口KOUT鍵盤完整編碼碼值輸出端口（七位二進制數(shù)）KOUT1掃描信號輸出端口（三位二進制數(shù)）SIN鍵盤消抖輸入端口（七位二進制數(shù)）SOUT鍵盤消抖輸出端口（七位二進制數(shù)）LIN鍵盤按鍵編碼模塊輸入端口（七位二進制數(shù)）DF數(shù)字按鍵標(biāo)志寄存器FF功能按鍵標(biāo)志寄存器ND數(shù)字按鍵識別編碼寄存器NF功能按鍵識別編碼寄存器LOCK電子密碼鎖上鎖狀態(tài)標(biāo)志寄存器LOCK1電子密碼鎖報警狀態(tài)標(biāo)志寄存器UNLOCK電子密碼鎖開鎖狀態(tài)標(biāo)志寄存器NULL1電子密碼鎖無密碼狀態(tài)標(biāo)志寄存器DATA電子密
2、碼鎖數(shù)碼顯示數(shù)據(jù)寄存器CAT電子密碼鎖數(shù)碼顯示位選寄存器33DISPLAY電子密碼鎖數(shù)碼顯示段選寄存器（十七位二進制數(shù)）NUM0、NUM1、NUM2、NUM3數(shù)碼顯示中分位顯示數(shù)據(jù)寄存器DISNUM數(shù)碼顯示段選數(shù)據(jù)寄存器I1數(shù)碼顯示計數(shù)器SCANS鍵盤掃描中按鍵完整編碼寄存器SCAN鍵盤掃描寄存器CNT鍵盤消抖計數(shù)器SIN1鍵盤按鍵鍵值寄存器I鍵盤掃描計數(shù)器DF1數(shù)字按鍵狀態(tài)標(biāo)志寄存器ACC鍵盤數(shù)字輸入暫存器T報警計數(shù)器REG電子密碼鎖密碼存儲器NC計數(shù)器1鍵盤輸入掃描部分源程序LIBRARYIEEE;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE
3、.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_1164.ALL;ENTITYkbscan1is33PORT(clk:inSTD_LOGIC;kin:inSTD_LOGIC_VECTOR(3DOWNTO0);---PC7-PC4kout:outSTD_LOGIC_VECTOR(7downto0);--PC3--PCkout1:outSTD_LOGIC_VECTOR(3downto0));endkbscan1;architectureaofkbscan1issignalscans:std_logic_vector(7downto0);--
4、PC7--PC0signalscan:std_logic_vector(3downto0);--PC3--PC0signalcnt:integerrange0to140;signalsin1:std_logic_vector(3downto0);signali:integerrange0to3;beginscans<=scan&kin;kout<=scans;kout1<=scan;process(clk)beginif(falling_edge(clk))thenif(i=3)theni<=0;elsei<=i+1;endif;caseiiswhen0=>scan<="
5、0001";when1=>scan<="0010";33when2=>scan<="0100";when3=>scan<="1000";endcase;endif;endprocess;Enda;2鍵盤輸入消抖部分源程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYxiaodouisPort(clk:inSTD_LOGIC;sin:instd_logic_vector(7downto0);sout:outstd_logic_vector(7downto0));endxiaodou;architecturebehavioralof
6、xiaodouissignalcnt:integerrange0to120;signalsin1:std_logic_vector(7downto0);beginprocess(clk)beginsin1<=sin;if(rising_edge(clk))thenif(sin1=sin)thencnt<=cnt+1;else33sin1<=sin;cnt<=0;endif;if(cnt=120)thensout<=sin;cnt<=0;endif;endif;endprocess;endbehavioral;3鍵盤輸入編碼部分源程序LIBRARYIEEE;USEIEEE.
7、STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_1164.ALL;ENTITYbianmaisPORT(clk:inSTD_LOGIC;lin:inSTD_LOGIC_VECTOR(7DOWNTO0);---PC7-PC4DF,FF:outstd_logic;nd,nf:BUFFERstd_logic_vector(3downto0));endbianma;architecturebofbianmaisbeginprocess(clk)b
