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《基于PCI總線(xiàn)信號(hào)數(shù)字復(fù)接系統(tǒng)——復(fù)接子系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)》由會(huì)員上傳分享，免費(fèi)在線(xiàn)閱讀，更多相關(guān)內(nèi)容在學(xué)術(shù)論文-天天文庫(kù)。
1、分類(lèi)號(hào)‘I盥!!LJI)【1工學(xué)碩士學(xué)位論文學(xué)號(hào)—j蟹041蜓王密級(jí)?，基于PCI總線(xiàn)信號(hào)數(shù)字復(fù)接系統(tǒng)——復(fù)接子系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)碩士生姓名一一王—塑磊學(xué)科專(zhuān)業(yè)信息與通信工程研究方向軍用無(wú)線(xiàn)通信與網(wǎng)絡(luò)技術(shù)指導(dǎo)教師王瑩教授國(guó)防科學(xué)技術(shù)大學(xué)研究生院二oo四年十一月國(guó)防科學(xué)技術(shù)入學(xué)研究生院學(xué)位論文ABSTRACTBusStructureISusedextensivelyindigitalsystemsforitsmodule—baseddesignmethodandsimplicityofsystemdesignandup
2、date．ButBusStructureneedsmanysignalwires，whichleadstomorecomplexsystems．Thisproblemcanbesovledbyadoptingthedigitalmultiplexingtechnology,whichcombinesseveralsignalwiresintoone．Inthedissertation，thedigitalmultiplexisdiscussedaimingattheschemeofComputerBusorothe
3、rIndustrialBus．Thesebasicnotionsofdigitalmultiplexaredeeplydiscussed，BusisintroducedandamethodofBusdigitalmultiplex，bythewayofFPGA，isexpatiateddetailedconnectedwithPCIBus．Atlast，allexampleoftheserialinterfaceofPCIBusistested．Theserialinterfaceiscompletedinsimp
4、leness．10wfrequencyandsteadyperformancewhichcombinesthesignalofcomputerinterfacafortheMagneticEnvironmentSimulationSystem．a(chǎn)doptsthecircuitarchitectureof“theexpertchip$5920ofthePCIbusinterface+FPGA”．usestheideaofdigitalmultiplexdiscussedaboveandkeepsthetopofcon
5、tr01softwareinterrupt．Notonlyamaterialdesignoftheserialinterfacebutalsoaappliedplanoftheinterfacehardwarecircuitarepresentedinthepaper．Theserialinterfacedesignedhasdebuggedwithreceivingendsuccessfullyandrealizedexpectantfunctions．Keywords：BusStructure，BusSigna
6、l，DigitalMultiplex，PCIBus，F(xiàn)PGA，ExpandingSerialInterface國(guó)防科學(xué)技術(shù)人學(xué)研究生院學(xué)位論文圖目錄圖1．1課題研究總體結(jié)構(gòu)框圖???????????圖2．1數(shù)字通信系統(tǒng)模型?????????????圖2．2數(shù)字復(fù)接系統(tǒng)方框圖????????????圖2．3準(zhǔn)同步復(fù)接器結(jié)構(gòu)示意圖??????????圖2．4數(shù)據(jù)幀塞入位囂和塞入指示示意圖??????圖2．5復(fù)接系統(tǒng)整體框圖?????????????圖3．1PCI總線(xiàn)微機(jī)系統(tǒng)方框圖??????????．圖3．2PCI總線(xiàn)
7、信號(hào)圖??????????????．圖3．3PCI總線(xiàn)讀操作時(shí)序圖???????????．圖3．4PCI總線(xiàn)寫(xiě)操作時(shí)序圖???????????圖3．5FPGA／CPLD基本原理圖??????????．．圖3．6總線(xiàn)信號(hào)進(jìn)入緩存器示意圖????????一圖3．7按位、按字復(fù)接示意圖???????????圖3．8信號(hào)復(fù)接數(shù)據(jù)處理流程圖??????????圖3．9信號(hào)復(fù)接數(shù)據(jù)處理流程圖??????????圖3．10一般總線(xiàn)信號(hào)復(fù)接流程圖?????????．圖4．1通信信號(hào)電磁環(huán)境模擬器接口寫(xiě)操作信號(hào)時(shí)序?圖4．2通信信號(hào)
8、電磁環(huán)境模擬器接口讀操作信號(hào)時(shí)序?圖4．3接口整體分塊圖??????????????圖4．4串行接口整體方框圖???????????．．圖4．5$5920內(nèi)部結(jié)構(gòu)圖????????????????圖4．6串行E2PROM與$5920接口????????圖4．7外加總線(xiàn)操作寄存器操作方式???????一圖4．8VIRTEXII系列產(chǎn)品結(jié)構(gòu)示意圖??????．圖
