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1、SouthChinaUniversityofTechnologySchoolofElectronicandinformationEngineeringIntegratedCircuitsDesignFinalExam,Spring2006B答案PleasewriteyourName,ClassandSIDinthefirstsheet.Usethespaceprovidedtoanswerallquestions.Name:Class__________SID________Grades______Problem1.Therearetenstatementsint
2、hissection,Foreachofthefollowingstatements,indicateitistrueorfalse.(15points)(T/F)(1)Thedepletion-regionwidthwillbeincreaseundertheforward-bias,correspondingtothechangeofspacecharge.(T/F)(2)Low-swingbusessavepowerandreducepropagationdelayatthesametime.(T/F)(3)MOSFETisaminoritycarrierd
3、evice.(T/F)(4)Afn-blockdynamicgatewillnothaveanychargesharingproblemsifonly0→1transitionsoccuratitsinputsduringevaluation.(T/F)(5)CheckthedataofVtisatypeofdiagnostictest.(T/F)(6)ThemainreasonforusingPMOStransistorinthePUNisthatPMOStransistorproduce“strongones”(T/F)(7)Theloadcapacitanc
4、eofastaticCMOSgatehasnoeffectonitsVTC.(T/F)(8)Decreasingsupplyvoltagehelpstoalleviatethevelocity-saturationproblem.(T/F)(9)ANAND-basedROMstructureistypicallymorecompactand8slowerthanaNOR-basedone.(T/F)(10)Thetaskofcircuitsynthesisistotranslatealogicdescriptionofacircuitintoanetworkoft
5、ransistorsthatmeetsasetoftimingconstraints.答案：1．F2.T3.T4.F5.F6．T7.F8.F9.T10.TProblem2:Therearefouranswersmarkeda),b),c),d)beneatheachquestion,Choosethebestanswer.(15points).(1).Thepinchedoffconditionatdrainregionis:a.VGS-VDS≤VTb.VGS-VDS≥VTc.VDS-VGSVT(2)Inordertoreducethe
6、propagationdelay,weshoulda.ReduceKpandKnb.ReduceVDDc.ReduceCLd.ReduceW/L(3)TheoutputtransitionprobabilitiesforthetwoinputstaticlogicANDgateis:a.(1-PA)(1-PB)b.(1-PAPB)PAPBc.1-PAPBd.(1-PA)(1-PB)[1-(1-PA)(1-PB)](4)Whengeneratingandoptimizingthecircuitschematicsorlayout,weneedusethefollo
7、wingtoolsfirst:a.Implementationandsynthesisb.Faultsimulationc.Testabilitytechniquesd.Analysisandverification(5)Whatisthelogicstyleofthefollowingfigure?a.PLAb.PALc.GALd.PROM8答案：1．a(chǎn)2.c3.b4.d5.aProblem3:Foreachofthefollowingstatements,pleaseafillinthecorrectanswer.(25points)(1)ParameterF
8、ullSc
