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1、浙江大學(xué)碩一L學(xué)位論文摘要了TLB和數(shù)據(jù)、指令訪問(wèn)高速緩存的資源沖突，減少緩存中TLB表項(xiàng)的訪問(wèn)次數(shù)。其中第一級(jí)TLB經(jīng)擴(kuò)展后可動(dòng)態(tài)支持兩種頁(yè)面大小，無(wú)需操作系統(tǒng)的支持，提升第一級(jí)TLB的命中率。實(shí)驗(yàn)結(jié)果表明，與傳統(tǒng)的TLB設(shè)計(jì)相比，應(yīng)用本方法的嵌入式處理器的功耗下降28．11％，面積減少21．58％，性能基本持平。本文提出的若干TLB關(guān)鍵技術(shù)對(duì)于嵌入式處理器提升性能、降低功耗、減小面積等具有積極的意義。關(guān)鍵詞嵌入式內(nèi)存管理單元；片上高速緩存；地址轉(zhuǎn)譯旁路緩沖器；資源復(fù)用；低功耗；編碼加鎖機(jī)制；動(dòng)態(tài)擴(kuò)展；多進(jìn)程共享；通用協(xié)處理器接1：2；協(xié)處理器擴(kuò)展浙江大學(xué)碩士學(xué)位論文Abstract
2、Withthedevelopmentofcomplicatedembeddedapplications，memorymanagementhasbecomethefocusandthedifficultpartofHW-SWdesigninhigh-endembeddedprocessors．Virtualmemorytechniqueisaneffectivememorymanagementmethod，whichistransparenttosoftwarebasedonoperatingsystem．Thiscansimplifythememorymanagementmodeand
3、enhancetheportabilityofapplicationsoftware．Meanwhile，memorymanagementunit(MMU)，themajorconcemofpowerconsumptionandareacostofembeddedprocessors，isimplementedinhardwaretorealizevirtualmemorytechnique．InthisthesisweproposesomekeytechniquesofembeddedTLBforhighperformanceandlowpowerimplementationofem
4、beddedMMU．Theoriginalcontributionsofthisthesisareasfollows：1．ATLBdesignmethodbasedoncacheresourcereusing．ThisthesisanalyzedthesimilaritybetweenTLBandCacheentryinstoragestructureandaccessingbehavior,andthenproposedanewTLBdesignmethodbasedonreusingcachehardwareresourceforlowerpowerconsumptionandsm
5、allerareacostinembeddedprocessor．Thismethodsetupcacheaddressmappingtable，whichrecordedthelocationofTLBentryinCache，todecreaseTLBaccesseswithlessdynamicpowerconsumption．2．Aninnovationofmulti-processTLBentrysharingonecachelinewindow．Thismethodpartitionscachelineintodifferentprocesswindowstoprevent
6、frequencyreplacementofTLBentryduringprocessswitch．Dynamical浙江人學(xué)碩士學(xué)位論文AbstractTLBentryextensionbasedoncachearchitectureenlargedthemappingrangeofphysicaladdressforhigherTLBhitrateandprovidedasolutiontoTLBentryrestrictionintraditionalTLBdesign．MoreoveLanentrylockingmethodofTLBwasalsoproposedtobalan
7、cetheresourcehazardinmaximumdegreebetweenTLBentryandinstruction／data．3．Two-levellow-powerTLBimplementationwithmultipleTLBpagesizessupported．Thismethodutilizedtwo-levelTLBarchitecturetosolvecacheaccesshazardbetweenTLBandinstr
