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1、modulesdram_input_efifo_module(//inputs:clk,rd,reset_n,wr,wr_data,//outputs:almost_empty,almost_full,empty,full,rd_data);outputalmost_empty;outputalmost_full;outputempty;outputfull;output[43:0]rd_data;inputclk;inputrd;inputreset_n;inputwr;input[43:0]wr_data;wirea
2、lmost_empty;wirealmost_full;wireempty;reg[1:0]entries;reg[43:0]entry_0;reg[43:0]entry_1;wirefull;regrd_address;reg[43:0]rd_data;wire[1:0]rdwr;regwr_address;assignrdwr={rd,wr};assignfull=entries==2;assignalmost_full=entries>=1;assignempty=entries==0;assignalmost_e
3、mpty=entries<=1;always@(entry_0orentry_1orrd_address)begincase(rd_address)//synthesisparallel_casefull_case1'd0:beginrd_data<=entry_0;end//1'd01'd1:beginrd_data<=entry_1;end//1'd1default:beginend//defaultendcase//rd_addressendalways@(posedgeclkornegedgereset_n)be
4、ginif(reset_n==0)beginwr_address<=0;rd_address<=0;entries<=0;endelsecase(rdwr)//synthesisparallel_casefull_case2'd1:begin//Writedataif(!full)beginentries<=entries+1;wr_address<=(wr_address==1)?0:(wr_address+1);endend//2'd12'd2:begin//Readdataif(!empty)beginentrie
5、s<=entries-1;rd_address<=(rd_address==1)?0:(rd_address+1);endend//2'd22'd3:beginwr_address<=(wr_address==1)?0:(wr_address+1);rd_address<=(rd_address==1)?0:(rd_address+1);end//2'd3default:beginend//defaultendcase//rdwrendalways@(posedgeclk)begin//Writedataif(wr&!f
6、ull)case(wr_address)//synthesisparallel_casefull_case1'd0:beginentry_0<=wr_data;end//1'd01'd1:beginentry_1<=wr_data;end//1'd1default:beginend//defaultendcase//wr_addressendendmodulemodulesdram(//inputs:az_addr,az_be_n,az_cs,az_data,az_rd_n,az_wr_n,clk,reset_n,//o
7、utputs:za_data,za_valid,za_waitrequest,zs_addr,zs_ba,zs_cas_n,zs_cke,zs_cs_n,zs_dq,zs_dqm,zs_ras_n,zs_we_n);output[15:0]za_data;outputza_valid;outputza_waitrequest;output[12:0]zs_addr;output[1:0]zs_ba;outputzs_cas_n;outputzs_cke;output[1:0]zs_cs_n;inout[15:0]zs_d
8、q;output[1:0]zs_dqm;outputzs_ras_n;outputzs_we_n;input[24:0]az_addr;input[1:0]az_be_n;inputaz_cs;input[15:0]az_data;inputaz_rd_n;inputaz_wr_n;inputclk;inputres
